FMAP: A Technology Mapping Algorithm for FPGA with MUX-LUT Mixed Architecture

Because of its advantages of the short design turnaround time and the convenience and low cost in integrated circuit prototyping and verification, the field programmable gate array (FPGA) has been widely utilized in many fields of electronic design. In this paper, a technology mapping algorithm for FPGA with MUX-LUT mixed architecture is presented. This algorithm, FMAP, is used in a design-aid software system for FPGA, which is developed specifically for an FPGA chip, FDP, with MUX-LUT mixed architecture. The bench marking result of technology mapping for FDP by FMAP is compared to the result of the Xilinx series by their own design system. The result is also presented in this paper.